This invention relates to a technique for generating a periodic function based on digital signals and, in particular, to a technique for generating a periodic function with reference to a function table. Such techniques are being used in the fields of, for example, audio, video, or communication signals processing.
According to one of such techniques known by the inventor, a unit angle stored in a register is repeatedly added in order to calculate a multiple of the unit angle and the amplitude of a periodic function corresponding to the multiple is referred to a function table.
Hereinbelow, description will be made with reference to FIG. 1 to a periodic function generating circuit based on such technique. First, a unit angle U, which is added to a multiple of the unit angle generated at previous clock, is stored in a register. Next, the unit angle U is added to a multiple S1 of the unit angle U currently stored in an accumulator by an adder. Then, an updated multiple S2=S1+U is stored in the accumulator. After that, an amplitude corresponding to the updated multiple S2 is referred to a function table previously stored in a function table ROM. These steps are repeatedly executed to generate a series of amplitude values, and finally, the periodic function shown in FIG. 2 is generated.
According to the periodic function generating circuit, when the unit angle U is a mixed number, namely the sum of an integer and a fraction, each fraction of the multiples S1, S2, . . . , Sn is dropped. Consequently, error of the multiple Sn gradually stacks up and increases. Furthermore, a repeating decimal is unavailable for the unit angle U because of its indefinite digits. If it is intended to set the sum of an integer and a repeating decimal as the unit angle U, the sum of the integer and an approximate value of the fraction is actually set as the unit angle U. In this case, the multiple Sn includes an inevitable margin of error, This error is independent of the calculating accuracy of the adder.
As shown in FIG. 3, stacking of errors of the multiple Sn causes phase difference between theoretical and output waveforms. The theoretical waveform drawn as a dotted line shows calculated one in theory. The output waveform drawn as a solid line shows one actually output from the periodic function generating circuit. It is noted that, as time passes, the phase difference stacks up and increases.
In order to restrict amount of the phase difference, the accumulator may be reset. In this case, a permitted limit of the phase difference is predetermined. When the multiple Sn stored in the accumulator is about to reach at the permitted limit, the accumulator is reset and the value stored in the accumulator is updated to zero. However, this causes discontinuity of phase at the reset point. As shown in FIG. 4, though the phase difference between the theoretical and output waveforms is canceled, the output waveform before the reset point is separated from the output waveform after the reset point nevertheless. Recently, considerable ones of digital circuit systems require strict management of phase for a long time. Therefore, to reset the accumulator is inappropriate for such recent systems.
Techniques related to the present invention are, for example, described in a Japanese Patent Publication (JP-B) No. H 7-43620, namely 43620/1995, and Japanese unexamined patent publications JP-A) numbers 2000-215029 and 200-196690, namely 215029/2000 and 196690/12000, respectively.